Programmable logic devices (PLDs) are a well-know type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they are less expensive and require less time to implement than semi-custom and custom integrated circuits.
One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks, or CLBs, that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that define how the CLBs, interconnections, and IOBs are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA from an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FPGAs can be reconfigured any number of times by simply reprogramming the configuration memory cells. Some FPGA applications take advantage of this feature by providing a number N of sets of configuration memory, each of which may be programmed to store a different set of configuration data. The FPGA may then be easily and quickly reprogrammed to function in one of N configurations. On the other hand, for an FPGA that has only one set of configuration memory, complex logic functions can be implemented by reconfiguring the FPGA to sequentially perform more than one logic function on a given set of input signals.
Unfortunately, each FPGA reconfiguration may require some or all of the following:
1. suspending the implementation of logic functions; PA1 2. loading a new bitstream of configuration data into an array of memory configuration cells in the FPGA; PA1 3. applying the saved state of the previous logic functions; PA1 4. allowing the logic levels of the newly reconfigured FPGA to settle to ensure valid data on the output pins before resuming operation; and PA1 5. saving the current state of the logic functions (e.g., saving the output levels of previous functions).
These steps are collectively time consuming, especially in applications that require frequent reconfiguration.
A partial solution to this speed problem involves integrating into a single chip or die the reconfiguration memory and read/write control circuitry associated with the FPGA. For a more detailed description of such a device, see U.S. Pat. No. 5,646,545, entitled "Time Multiplexed Programmable Logic Device," issued Jul. 8, 1997, which is incorporated herein by reference.
Integrating the configuration memory and read/write control circuitry with the FPGA solves many problems associated with dynamic reconfiguration. However, there is still substantial room for improvement. For example, settling time can still impose a substantial delay in applications that require frequent reconfiguration. Moreover, the reconfiguration memory and associated read/write control circuitry occupy a large percentage of available chip area. In one example having eight alternative configurations, the additional memory and resources increase the area of the FPGA by a factor of three. Increasing the area is expensive and slows the logic function of the FPGA. Finally, reading hundreds of thousands of memory locations, as is required for a typical reconfiguration, consumes substantial power. The resulting heat can adversely affect reliability and speed performance.
Also, some FPGAs must go into a configuration mode while being configured. If only a small part of the device is being configured, this time can be small, but it must be accounted for nevertheless, and therefore any reconfiguration causes a disruption in the device operation while the reconfiguration is taking place.